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Dwarkesh Podcast · 2 min · Oct 22, 2026

Backside power makes high-NA EUV more useful for Intel

Backside power relaxes Intel's front-side pitch needs, letting high-NA print some patterns in one pass. TSMC needs double patterning, while Intel leaves high-NA as a customer-by-customer option.

CO

Chris Oth

  • Dwarkesh Patel, Host · Host, Dwarkesh Podcast

    Co-wrote The Scaling Era, an oral history of AI; named to TIME100 AI.

About this segment

Backside power relaxes Intel's front-side pitch needs, letting high-NA print some patterns in one pass. TSMC needs double patterning, while Intel leaves high-NA as a customer-by-customer option.

From “What will computer chips look like in 2045?”, Oct 22, 2026. Watch the full episode

“We use backside power. That means that you actually alleviate some of the pitch requirements you have on the front side.”
COChris Othat 14:51 · Dwarkesh Podcast14:51

Takeaways

  1. Backside power frees space on the front side.
  2. Intel can print some patterns with one high-NA pass.
  3. Intel handles 14A high-NA use as a customer option.
Watch 2:18 from 14:24

In this episode

Full episode
  1. 47:57Tool shortages cap leading-edge chip output near 2x5:18
  2. 32:37Stacked transistors need years of process development7:08
  3. 1:02:43The fab industry may need to rethink its basic assumptions5:00
  4. 55:13Intel says scale and execution are its main gaps to TSMC3:58

  5. 14:24Backside power makes high-NA EUV more useful for Intel2:18

  6. 23:42Intel's process team makes decisions before data is complete2:57Up next
  7. 43:50Hybrid bonding has demonstrated submicron connection pitches3:18
  8. 2:54Intel learned to limit how much innovation goes into each node2:47

Transcript

Transcribed by machine (Whisper) from the episode’s audio, so a word may be off here and there.

  1. 14:26

    Now you guys are using high NA UV tools for 14A, whereas TSMC has said that they don't make economical sense yet for them. How do you decide whether the next litho tool is the one that is ready to adopt or not? Yeah, and high NA is a good example of where because of the architecture of our technology versus TSMC, we make different conclusions off of the same tool set. We use backside power. That means that you actually alleviate some of the pitch requirements you have on the front side.

  2. 15:01

    And that allows you to print that directly with high NA. TSMC has to run very tighter pitches because they don't have backside power and they can't do that with high NA. So they have to use double patterning EV. So for them, it's not very helpful. For us, it is very helpful. Now at 14, we've left it as an option and it's something that we'll have a discussion with the customer on because there's some value proposition of it. There's some complexity that it adds. Chris is referring to a feature called backside power. A chip has two different kinds of wiring. Power lines deliver electricity to the transistors, and they need to be thick.

  3. 15:35

    Signal lines let the transistors talk to each other. They're much thinner, but they need to be spaced apart so that the signal from one wire doesn't interfere with the signal from another. In the past, all of these power lines and signal lines had to be crammed together on top of the transistors. Intel's newest process moves these power lines below the transistors, to the back of the wafer. This frees up space on top, so the signal lines don't have to be packed as tightly.

  4. 16:00

    This change makes high NA worth it for Intel. Without backside power, the wiring is so tight that it would require multiple passes to print, even with high NA. With backside power, a single high NA pass is enough. Outside companies can now commission Intel to manufacture chips that they've designed. They follow Intel's Process Design Kit, or PDK, the menu of what a given process can build and the rules for building it. Do you need to lock that into your PDK right now for customers who are planning on developing on 14A?

  5. 16:30

    It's an option in the PDK today, and we're handling it as a customer-by-customer discussion that we have as to whether or not they want to go down that path or not. So for 18A, there was public reporting that there were delays