Hybrid bonding has demonstrated submicron connection pitches

Transcript

Transcribed by machine (Whisper) from the episode’s audio, so a word may be off here and there.

1. 43:52

   Two different ways you could do hybrid bonding is die to die and die to wafer And maybe we can talk about the advantage of both and which one actually practically works better sure so actually around intel typically i think as you're referring to die to die we typically call it wafer to wafer so we actually take a full wafer and another wafer and bond them together that's an approach that's really popular right now in the cmos image sensor industry in fact basically dominates it and it's being looked at for other things like memory stacking all kinds of stuff people have published ideas about one of the challenges with that though is that you need dyes that perfectly match each other and are perfectly like left-handed and right-handed, right?

2. 44:32

   So you have to be able to pull on exactly one to the other. So one-to-one die size is a challenge. So if they're not the exact same design device on top and bottom, that's a problem. So wafer to wafer, it's just challenging to make sure that you have wafers that match really well in terms of the sort, right? So sort good array here versus sort good array here. If they match exactly good die and bad die that they all match, I can get 100% yield of that operation of the good dies.

3. 44:55

   But the chances of that are very low. it's going to be some randomization of the two and whatever that randomization is is just going to be loss of good batting batting bonding to bad whereas at chipped a wafer i can dictate the terms right i can singulate and have known good dyes that i've tested at the chip level and then only bond known good to a known good base position do you think then chipped a wafer is the way that you'll do hyperbonding in the future i think we're going to do both we definitely have the capability to do both it's really customer and architecture driven but certainly chipped a wafer the logic to logic space makes a lot of sense. So you were explaining that going from advanced packaging to hybrid bonding, the size of the pitches is decreasing. How much further could

4. 45:35

   that go? That's a wonderful question. So, you know, historically, like we were saying 15 years ago, first level interconnect was 130, 150 micrometer pitch. Today in HVM, we're doing 25 micrometer pitch in Fulveros. Here we're doing sub 10, but there's already been literature out there. In fact, The biggest conference every year in packaging is the IEEE ECTC conference that happens in May. And there was a paper there this year showing reliability data on a 0.45 micron pitch hybrid bonded device.

5. 46:06

   So you can imagine that's a whole nother order of magnitude and density, again, from where we are right now on HBI and scalability that's already been proven. So I see a long runway there. Within interconnect, within a single wafer, how far separated are they usually? So the back end of the fab, you can imagine, like the few layers below packaging are typically around one micron to a half micron in size.

6. 46:33

   So if you can push packaging down to 0.5 microns or below, we can start, you can almost think about taking layers off the top of the die and connecting to a lower layer within the silicon to another lower layer within the silicon, right? That's really kind of where the beauty of hybrid bonding happens. You could think someday about even having reduced interconnect layers on both sides that we can bond together and have less total you know ir drop between the two transistor layers it's really kind of cool to think about where that could go once we get into those regimes actually i am very curious about for ai it makes sense why hyperbonding is so